There is a constant motivation to reduce the active power and/or standby power of semiconductor chips and macros. This current focus is dictated by the increased proliferation of semiconductors in mobile and portable applications. Therefore, a need exists for intelligent power management on memory chips and macros.
In the past power management of memory refresh operations has been described in U.S. Pat. No. 4,120,047 of Varadi entitled “Quasi-Static MOS Memory Array With Standby Operation. The Varadi patent describes a MOSFET″ memory array that uses a single voltage source (i.e., 5 volts) and operates basically as a static memory array rather than as a dynamic memory array that requires the gates of the MOS devices of the memory array to be periodically refreshed to restore or refresh the memory states contained therein. Each of the memory cells of the memory array contains four MOS devices that are cross-coupled into a flip-flop type of memory cell. All of the memory cells connected to a common word line are also connected to a common return line to which is connected a single resistor and a single large MOS or FET device. The large MOS device is turned on during the active operation of the memory array (during write and read operations) and is turned off during the standby operation of the memory array. The resistor functions to insure that some current flow takes place, during the standby operation, from all the memory cells connected to the common return line in order to maintain the data states (“1” or “0”) in each of the memory cells.” In the intervening years since the issuance of the Varadi patent we have found that there remains a need for a method and device for providing low power standby operation that occupies less silicon area and is applicable to word-line driver architectures as well.
U.S. Pat. No. 6,236,617 of Hsu et al. entitled “High Performance CMOS Wordline Driver” describes a wordline DRAM array having n groups of m wordlines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage and one driver circuit in each group is exposed to a boosted wordline high voltage greater than the circuit high voltage), in which the wordline driver circuits have an output stage comprising a standard NFET in series with a high threshold voltage PFET. In the example shown there are 1024 wordline drivers and a row (group) decoder “100” which drives the gates of a selected group of four of those wordline drivers. A wordline selector “200” provides an input to the source of a PFET transistor connected in series to a parallel pair of NFET transistors, one of which has its gate connected to the row (group) decoder and the other one of which has its gate connected to a restore circuit. The driver passes voltage Vpp on to a wordline, since WLDV connected to that driver is at Vpp. However, for the remaining (m−1) drivers in that group, the WLDV signals are kept at the Vm (e.g. 0.7V) level and even though the gates of those drivers are pulled low, the high Vt (about −1.2V) of the PFET device, will not prevent the output of those drivers from being maintained by the restore circuit at a negative level (or −0.5V.) The restore circuit opens a path between a terminal and the wordline to restore the quiescent state on the wordline block.
U.S. Pat. No. 6,426,914 of Dennard et al. entitled “Floating Wordline Using A Dynamic Row Decoder And Bitline VDD Precharge” describes a “wordline driver D consisting of a pull-up pMOS PU, a pull-down MOS PD, and a second nMOS pull-down device K which is called a killer device. This killer device is used to deselect the half-selected wordlines so they will not be floating.” Dennard et al states further that “each decoded output from a level shifter is tied to a group of four wordline drivers. One of the four wordline drivers is selected by decoding the sources of the pull-up pMOS devices as well as the gates of the killer devices.”
FIGS. 1A and 1B describe a prior art DRAM memory configuration with the problem of excessive consumption of power during standby operation.
FIG. 1A shows a prior art memory configuration for multi-banked a DRAM 10. The DRAM 8 includes a set of Second Sense Amplifiers (SSA) 11 and sixteen (16) banks 120, 121, 12X, 133, 134, and 135.
Referring to Second Sense Amplifiers (SSA) 11, Hanson et al. U.S. Pat. No. 6,115,308 entitled “Sense Amplifier and Method of Using the Same with Pipelined Read, Restore and Write Operations” describes a second sense amplifier memory device which may have a sense amplifier circuit and two drivers connected to the sense amplifier circuit. Two data bus lines may be connected to the sense amplifier circuit to receive data signals. A first equalize signal and a second equalize signal are applied to the sense amplifier circuit to allow the sense amplifier circuit to receive the data signals across the data bus lines. A switch signal is applied to the sense amplifier circuit to connect the data bus lines to a read data bus. The state of the first equalize signal is changed so that the data bus lines either receive new data or the data bus lines are equalized to a predetermined voltage while the data is on the read data bus and is capable of being read.
As additional background for this invention, the row architecture of one of the banks 12X of a DRAM 10, which is shown some in detail in FIG. 1B, is described next. The row path is comprised of three key blocks; the RDEC (Row address DECoder) block 14, the RSEL (Row SELector level shifter as in Dennard et al.) block 16, and the row or WLDRV (WordLine DRiVer) block 18 in which there are 128, i.e. (X+1), wordline blocks WLDRV, e.g. wordline blocks DR1 to DR512 for control codes WLDRV<0>, WLDRV<1>, WLDRV<2>, WLDRV<3>, z,900 WLDRV<X> where X=511. In response to control codes from a data processing system (not shown), the RDEC block 14 and the RSEL block 16 perform a process of hierarchical decoding. First, the RDEC block 14 enables the selection of four (4) wordlines out of the total number of 512 wordlines WLDRV<0>, WLDRV<1>, WLDRV<2>, WLDRV<3>>, z,900 WLDRV<127>. For the example of 512 rows in a bank, the RDEC performs a 1/128 decode. Then the RSEL block 16 performs the final ¼ decode with a two-bit predecoder (not shown) to activate one (1) of the four WLDRV blocks activated by the RDEC block 14 with a signal on one of the WLDV lines 20A–20D. For example referring to FIG. 2 the RSEL in FIG. 1B can employ the a two-bit predecoder (not shown) to activate line 20A, which is one of the four wordline drivers 20A–20D. Thus, the row selector RSEL block 16 has a selector line 20A–20D connected to n/2x of the wordline drivers in the group of n wordline drivers, where x=is an integer greater than 1, e.g. the selector line is connected to n/4 or n/8 of the wordline drivers. The signal on the WLDECN bus line performs the 1/128 decode, enabling four WLDRVs with horizontal buses. In summary, the RDEC block 14 sends a signal on lines WLDEC-1 to WLDEC-128 to select four WLDRV units. For example, as shown by FIG. 1B, line WLDEC-1 line 15-1 is connected so that it can simultaneously energize four wordline drivers WLDRV<0:3>, i.e. WLDRV<0>, WLDRV<1>, WLDRV<2>, WLDRV<3>) from the set of the 512 wordlines with the signal on the WLDECN (WordLine DECoder Signal @ low) line to perform a 1/32 decode. The WLDECN-128 line 15-128 can energize the last four wordline drivers WLDRV<508> driver (not shown), WLDRV<509> driver (not shown), WLDRV<510> driver (not shown), and WLDRV<511> driver DR512 which is the only one of the four shown in FIG. 1B for convenience of illustration.
Then the RSEL block 16 decodes a one (1) out of the four (4) signals from the data processing system (not shown) to select one of the four wordlines enabled by the RDEC block 14. The RSEL block 16 then encodes signals on vertical Word Line DriVe (WLDV) lines 20A–20D to enable ¼ of the Word Line DriVe (WLDRV) blocks with signals on WLDV lines 20A–20D. The output of the RSEL block, ¼ of the WLDV bus lines 20A–20D will be active while at the same time ¾ of the Word Line ReSeT (WLRST) bus lines 22A–22D will be activated to ensure the deactivation of the remaining ¾ of the wordline blocks WLDRV. In the current state of the art of multi-banked DRAMs and embedded DRAMs, the process of wordline decoding is performed hierarchically.
The non-activated wordlines are held low by three (3) out of four (4) of the Wordline Reset signals (WLRST<0:3>) on wordline bus lines 22A–22D. For example, if WLDRV<0> is to be selected, the value on line 20A for the code WLDV<0> will be high. In addition the value on bus lines 22A–22D for the three codes WLRST<1:3> will be high, the three codes WLDV<1:3> will be low, and for the single code WLRST<0>> line 22A will be high.
FIG. 2 shows a portion 18″ of the WLDRV block 18″ of FIG. 1B which includes two of the prior art wordline driver circuits DR1 and DR2 plus BL<0> bitline 28, and two array transistor circuits A0/A1 with two related array capacitors C1/C2.
Block DR1 includes pull-up PFET transistor P1, pull-down NFET transistor N1 and killer NFET transistor N2. For the pull-up PFET P1 the source is connected to WLDV<0> line 20A and the drain is connected to node B2, as are the drains of the pull-down NFET N1 and the killer NFET N2. The gates of transistors P1 and N1 are connected via node B1 to WLDECN line 15-1. The gate of NFET N2 is connected to WLRST<0> line 22A. The sources of the pull-down and killer transistors N1 and N2 are connected to ground (reference potential). The drains of transistors P1, N1 and N2 are all connected via node B2 to the wordline output WL<0> line 26-1 which connects to the gate of NFET array transistor A0 which has its source connected to the array capacitor C1 (connected to ground) and its drain connected to node B5, which is the BL<0> line 28.
Block DR2 includes pull-up PFET transistor P2 and pull-down NFET transistor N3 and killer NFET transistor N4. For PFET P2 the source is connected to WLDV<1> line 20B and the drain is connected to node B4, as are the drains of transistors N3 and N4. As in block DR1, the gates of transistors P2 and N3 are connected via node B3 to WLDECN line 15-1. The gate of transistor N4 is connected to WLRST<1> line 22B. The sources of transistors N3 and N4 are connected to ground (reference potential). The drains of transistors P2, N3 and N4 are connected via node B4 to the wordline output WL<1> line 26-2 which connects to the gate of NFET array transistor A1 which has its source connected to the array capacitor C2 (connected to ground) and its drain (like the drain of NFET array transistor A0) is also connected to node B5, which is the BL<0> line 28. Examples of voltages applied to the circuit are VDD which has a value of about 1.2V, Vpp which varies between a value of 0V and about 1.5V to 2.5V and WLRST which varies between about 0V and VDD, i.e. 1.2V. The value of WLDV<0> is shown to be VPP (e.g. 2.5V) after rising from 0V. The value of WLDV<1> is shown to be 0V after falling from VPP (e.g. 2.5V).
As stated above with respect to FIG. 1B, in the RSEL 16 a two predecoder (not shown is used to activate line 20A which is one of the four wordline drivers 20A–20D. Then referring to FIG. 2, in order to activate WL<0> line 26-1, the source of the PMOS pull device P1 is tied to VPP, while the gate of the killer device is tied to Ground on line 22A. At this moment, the sources of the other three pMOS pull devices in drivers DR1, DR2, DR3 and DR4 stay at ground, and the gates of the other three killer devices stay at VDD. This second level decoding is applied to all the wordline drivers in the first level decoded group of four.
Referring to FIG. 2 and the above example, the signal on the shared WLDECN line 15-1 from the RDEC block 14 in FIG. 1B is low, preventing NFET transistors N1 in driver DR1 WLDRV<0> and N3 in WLDRV<1> in driver DR2 from conducting. The input for code WLDV<1> on line 20B to the source circuit of PFET P2 in driver DR2 will be low; and for the gate terminal of NFET N4 single code WLRST<1> in driver DR2 the value will be high, preventing the PFET P2 from conducting and enabling the NFET N4 in driver DR2 to conduct, respectively. The input WLDV<0> on the source terminal of the PFET P1 is high enabling the PFET P1 to conduct and to charge the WL<0> wordline 26-1, up to VPP, its boosted logic level ‘1’. The reset value on bus 22B for code WLRST<1> would be high on the gate of the NFET N4, thereby enabling the NFET N4 to conduct and to discharge the wordline 26-2, WL<1> up to ground, which is its logic level ‘0’. The activated WL<0> wordline 26-1 drives the gate of the array transistor PFET A1 to read data from or to write data into the memory element.
When the memory array is placed in a standby state, none of the wordlines are activated. Therefore, in that case, all of the array transistor gates will be at the logic level “0” or ground.